PURPOSE: To attain high speed adaptive discrete cosine transformation(DCT) arithmetic processing and to simplify the circuit configuration of the DCT arithmetic device by providing a shaft register implementing multiplying processing of a supplied data in the arithmetic device.

CONSTITUTION: An input picture data is fed to the input of four shift registers 170a-170d being components of a shift register 170. A clock signal designating a shift quantity and a shift direction corresponding to a cosine coefficient is fed to each of the shift registers 170a-170d. Then each of the shift registers 170a-170d implements shifting the input data. An adder 81 adds the shift result data to output a picture data being a prescribed multiple of the input picture data. Furthermore, a shift register 171 is configurated similarly to the shift register 170. Since the multiplication processing of the picture data is implemented by the shift operation only, the time required for the multiplication processing is reduced.