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Patent Searching and Data


Title:
OUTLINE WIRING DETERMINATION METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH0786406
Kind Code:
A
Abstract:

PURPOSE: To obtain an outline wiring path, by measuring the shortest distance from the whole nodes on a channel graph to the whole elements, and sequentially performing a searching process of wiring path, an ordering process of wiring path, and a combination selection process of optimum wiring path.

CONSTITUTION: Each element is surrounded by channels C1-C18 which abstract regions capable of wiring between elements, and connected through each of the nodes N1-N13. A cost table showing the shortest distance from nodes N1-N49 to nodes N1a, N1b, N1c-N6a, N6b, N6c on the whole terminals is formed. By a branch and bound method wherein the cost table is used, all of the wiring path candidates for each net are listed up. By referring the number of the wiring path candidates, the order of nets performing a wiring process is determined. One wiring path is selected out of the wiring path candidates for each net, in the order of net whose wiring process order is determined for all nets by the branch and bound method. Thereby an outline wiring path can be obtained.


Inventors:
TSUBOTA TADANAO
Application Number:
JP18259393A
Publication Date:
March 31, 1995
Filing Date:
July 23, 1993
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/82; G06F17/50; G06T7/00; (IPC1-7): H01L21/82; G06T7/00
Attorney, Agent or Firm:
Kazuo Sato (3 others)