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Patent Searching and Data


Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP2012191671
Kind Code:
A
Abstract:

To provide an output buffer circuit that suppresses increases in the area, volume and number of components of output buffers and improves drive capability.

In an output buffer circuit 1 having a first input path 4a for transmitting a first drive signal LIN, a second input path 4b for transmitting a second drive signal RIN, a first output buffer 6a corresponding to the first input path 4a, and a second output buffer 6b corresponding to the second input path 4b, input path switching means 8 electrically connects the first input path 4a to the first output buffer 6a and second output buffer 6b in a monaural mode out of stereo and monaural modes, and output path switching means 10 electrically connects the first output buffer 6a and second output buffer 6b to a first load 2a corresponding to the first input path 4a and first output buffer 6a.


Inventors:
AIZAWA HIDEYUKI
Application Number:
JP2012146267A
Publication Date:
October 04, 2012
Filing Date:
June 29, 2012
Export Citation:
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Assignee:
ASAHI KASEI DENSHI KK
International Classes:
H03F3/68; H03F3/187; H03F3/21; H03K17/00; H03K17/687; H03K17/693; H03K19/0175; H03K19/0948
Domestic Patent References:
JPS4946701A1974-05-04
JPH05226948A1993-09-03
Attorney, Agent or Firm:
小西 恵
森 哲也
田中 秀▲てつ▼