Title:
OUTPUT CLAMP CIRCUIT
Document Type and Number:
Japanese Patent JP3704219
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain an output clamp circuit by which a clamp voltage independent of power supply voltage fluctuation is obtained and a clamp voltage is not fluctuated by an output current.
SOLUTION: In the case that a clamp voltage is applied to bases of transistors(TRs) Q1, Q2 of an output Darlington circuit with a reference voltage generated by a constant current from a constant current source, TRs Q4-Q6 are provided to configure an emitter follower of a prescribed stage number with respect to bases on the TRs Q1, Q2 of the output Darlington circuit. The number of the stages of the TRs Q4-Q6 configuring the emitter follower is changed, according to an output current value to suppress fluctuation in the clamp voltage depending on the output current value.
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Inventors:
Hiroyoshi Kawahara
Ono Yukio
Ono Yukio
Application Number:
JP1028797A
Publication Date:
October 12, 2005
Filing Date:
January 23, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L27/04; G05F3/22; H01L21/822; H03G11/00; H03K5/007; (IPC1-7): H03G11/00; G05F3/22; H01L21/822; H01L27/04; H03K5/007
Domestic Patent References:
| JP5014767A | ||||
| JP5327429A |
Attorney, Agent or Firm:
Takenaka Ikuo
Masuo Oiwa
Toshihide Kodama
Keigo Murakami
Masuo Oiwa
Toshihide Kodama
Keigo Murakami
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