Title:
PACKAGE FOR HOUSING OF OPTICAL SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3426717
Kind Code:
B2
Abstract:
PURPOSE: To accurately position lead wires on a metallized wiring layer, and to prevent them from connection by shifting by a method wherein a through hole or a notch, where the lead wire can be passed through, is provided on the metallized wiring layer where the electrode of a Peltier element of ceramic terminal member is electrically connected through the lead wire.
CONSTITUTION: A plurality of metallized wirings 11, which are extending from the inside to the outside of a metal frame 2, are deposited on the upper surface of the protruding parts 3a and 3b of a ceramic terminal member 3. On the inside part of the metal frame 2 of the metallized wiring layer 11, each electrode of an optical semiconductor element 6 is electrically connected through a bonding wire 12, and lead wires 13, connected to the electrode of a Peltier element 8, are electrically connected through solder. Besides, on the ceramic terminal part member 3, through holes 3d are formed on the region where the lead wires 13, connected to the electrode of the Peltier element 8, are electrically connected through solder. Besides, on the ceramic terminal part member 3, through holes 3d are formed on the region where the lead wires 13, connected to the electrode of the Peltier element 8 by the protruding part 3a, is soldered.
Inventors:
Yoshiaki Ueda
Application Number:
JP17063094A
Publication Date:
July 14, 2003
Filing Date:
July 22, 1994
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H01L23/28; G02B6/42; H01L23/02; H01L31/0232; H01S5/00; (IPC1-7): H01L23/02; H01L23/28; H01L31/0232
Domestic Patent References:
| JP1289129A | ||||
| JP63280446A | ||||
| JP548460A | ||||
| JP4246847A | ||||
| JP5944099U | ||||
| JP5944100U | ||||
| JP2142538U | ||||
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