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Patent Searching and Data


Title:
PACKAGE FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS568854
Kind Code:
A
Abstract:

PURPOSE: To limit the substrate voltage variation within a small value in a semiconductor 1C which is integrated accompanied by a substrate voltage generating circuit without addition of externally added capacitor by a capacitor being integrated within a package.

CONSTITUTION: Beneath a die pad region C in a package where packaging materials are piled up, a connecting plate E which is connected with an electrode A0 which is connected with a power source is installed within it. A semiconductor device which is integrated accompanied by a substrate voltage generating circuit has a die pad region covered with a conductor all over it, and on them a semiconductor chip is placed. And for energizing the substrate by a voltage generated on the semiconductor device's surface there is a connection by a wiring material D between die pad regions. In this constitution a capacitor can be formed between the die pad region and the electrode plate E having insulation materials between them. By this consitution a voltage terminal on the semiconductor device's surface have a large capacitance for generating voltages, and a substrate voltage is able to have a small variation.


Inventors:
SHIMOTORI KAZUHIRO
NAGAYAMA YASUHARU
NAKANO TAKAO
Application Number:
JP8603279A
Publication Date:
January 29, 1981
Filing Date:
July 04, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L23/12; H01L23/64; H01L25/00; (IPC1-7): H01L23/12; H01L23/52