Title:
NONVOLATILE SEMICONDUCTOR STORAGE
Document Type and Number:
Japanese Patent JP3212396
Kind Code:
B2
Abstract:
PURPOSE: To attain normally reading the stored data even when power source is applied even in the case of improving an operation speed by detecting the change of an address signal and the throwing in of power source and performing the operation of the charge-up, etc., of a bit line.
CONSTITUTION: The power source voltage VCC, and the high voltage VPP, are fixed at the time of verify read operation. Then, the signals /INT and / INTATD outputted from a power source circuit 33 are H as it is. When reading operation is started, any one between EVD and WVD is raised according to the operational contents. Verify voltages RVPC and PSSA are outputted according to that and applied to prescribed parts of a row decoder 13 and a sense amplifier 18. When an address signal is changed, an address transition detective signal is outputted by an ATD circuit 31, and an ATD signal is outputted by an ATD synthesis circuit 32. After the charge-up of the bit line is performed according to that, the data are read from an access memory. At the time of reading when power source is applied, normal read is performed since source voltage at the time is higher than the verify voltage at an erasure time.
Inventors:
Hiromi Kawashima
Takao Akaogi
Takao Akaogi
Application Number:
JP495593A
Publication Date:
September 25, 2001
Filing Date:
January 14, 1993
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C16/02; G11C5/14; G11C16/06; G11C16/30; G11C16/34; H01L21/8247; H01L27/115; (IPC1-7): G11C16/02; G11C16/06
Domestic Patent References:
| JP593792A | ||||
| JP63268200A | ||||
| JP62154082A | ||||
| JP6488998A | ||||
| JP57152696U |
Attorney, Agent or Firm:
Shoichi Ui (4 others)