Title:
パラレル/シリアル変換回路、光出力制御回路、および光記録装置
Document Type and Number:
Japanese Patent JP4016946
Kind Code:
B2
Abstract:
A high speed, high accuracy parallel/serial conversion circuit, wherein a PLL circuit 50 receives as input and locks a clock CLK, supplies the same to different parts of an apparatus; the PLL circuit 50 controls a 16-tap ring oscillator 60 to shift the phase of a clock frequency-locked to a reference clock so as to generate 32 types of phase shift pulses CK0 to CK31 shifted in phase by increments of 1/32 of the clock width from the reference clock by the differential outputs of the 16 taps and supplies the same to a P/S conversion circuit 70; and the P/S conversion circuit 70 generates fine width pulses with 1/32 pulse widths based on the 32 types of phase shift pulses shifted in phase by increments of 1/32. Further, the fine width pulses are used to convert parallel signals output from a RAM 30 and a decoder 40 to a serial signal.
Inventors:
Koichi Yokoyama
Katsunori Sato
Katsunori Sato
Application Number:
JP2003531617A
Publication Date:
December 05, 2007
Filing Date:
September 25, 2002
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H03M9/00; G11B7/125; G11B7/126; G11B20/10; G11C11/417; G11B7/0045; G11B7/006; G11B7/007
Domestic Patent References:
| JP1317026A | ||||
| JP7153080A |
Attorney, Agent or Firm:
Takahisa Sato