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Title:
PARITY CHECK SYSTEM OF SEMI-FIXED DATA
Document Type and Number:
Japanese Patent JPS6077530
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of data read by storing a parity bit generated based on a data of a semi-fixed data group at the initial operation and comparing it with a parity bit generated at a normal operating state.

CONSTITUTION: An RAM3 is controlled to a write mode WE by an initial operating signal INT. When a semi-fixed data group 1 is read next, a parity bit is generated by a parity generation circuit 2 and written in the RAM3. Then the RAM3 is controlled to the read mode. In reading the data group 1, the parity bit is generated by the circuit 2. Then a comparator circuit 5 compares the parity bit generated at the initial state with the parity bit generated at the normal state. The reliability of data read is improved by comparing both parity bits and checking the difference.


Inventors:
TANIGUCHI TOORU
TOMIZAWA SHINICHI
ICHIKI TOORU
Application Number:
JP18616483A
Publication Date:
May 02, 1985
Filing Date:
October 05, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M13/00; G06F11/10; H03M13/09; (IPC1-7): G06F11/00
Attorney, Agent or Firm:
Sadaichi Igita