PURPOSE: To obtain the performance of the titled processor which is coincident with the set performance by controlling the performance of an arithmetic unit in response to an arithmetic execution signal with an indication given to an arithmetic control means for the arithmetic idle processing set previously, therefore, producing an idle time to the arithmetic execution.

CONSTITUTION: A register 37 holds a microinstruction read out of a control storage CS, and a decoder 38 decodes the microinstruction when a latch 32 is set (-E×B=0) to control the execution of an arithmetic unit. When a suppression signal FWAIT given from a performance control circuit is set at 1, a latch EXB32 is set at 0 for suppression of the signal FWAIT. Then the signal WAIT is sent to a latch EXC33 after half cycle and kept at '0' for a cycle. When the signal FWAIT is released, the contents '1' of a latch EXA31 are sent to the EXB32 for repetition of an operation where the signal FWAIT is delivered by a cycle when the EXB32 is delivered by two cycles. As a result, the operation is executed just in a cycle of the EXB and the arithmetic time is equal to a cycle of the signal FWAIT.