PURPOSE: To obtain a phase inversion detection signal having a signal waveform of high S/N by performing the coincidence logic operation between a digital reception signal and a delayed signal and outputting the signal, where states of logical level '0' and logical level '1' are inverted, as the phase inversion detection signal in response to the coincidence logical operation result signal.

CONSTITUTION: One of two branched signals from a first branching circuit 1 is supplied to a first delay circuit 2 and is delayed by a time (t) corresponding to one bit of a digital carrier signal DC to output a delayed digital signal B. This signal B and the other digital reception signal A which is not delayed are supplied to an exclusive NOR (coincidence logic) gate 3. A coincidence logical operation result signal C is supplied to a second branching circuit 4 and is delayed in a delay circuit 5 by a half period of a modulation signal MS, namely, (1/2)T, and this delay signal and the original coincidence logical operation result signal C are supplied to an AND gate 6, and AND between them is taken. A phase inversion detection signal (reproduced signal) F is outputted by repeated turning-on/off in accordance with phase inversion points of the digital reception signal A in response to an AND result signal E.