PURPOSE: To reduce the phase jitter by dividing an input clock with a prescribed dividing ratio to obtain two low frequency clocks having a difference of phase by an amount equivalent to the pulse width of the input clock and selecting either one of both clocks.
CONSTITUTION: When an input clock Ci is divided by a counter circuit CNT and the count value "5" is obtained, both a delay detection signal (b) and an advance detection signal (f) are fetched by flip-flops FF1 and FF0. The circuit CNT is set to measure the phase cycle of a low frequency clock C1. In this case, a low frequency clock C2 which is delayed by an amount equivalent to the width of the input clock is produced by a flip-flop FF2 which works on an inverted signal of the input clock. Then a flip-flop FF3 actuates a selection circuit SEL when signals (b) and (f) are detected, and a low frequency clock different from that selected previously is delivered. Thus the control is possible within a cycle of the input clock.
KAMATA HAJIME
KATOU YUUJI
