PURPOSE: To prevent production of a pattern of consecutive zeros by providing an exclusive OR circuit in which output of an output signal from a predetermined circuit stage is fed back to a shift register and a logic circuit feeding back a '1' signal to the shift register when an output signal of all circuit stages of the shift register is '0'.

CONSTITUTION: An output of an exclusive OR circuit 6-4 is fed back to a 1st stage flip-flop 2-1 of a shift register 4 via an OR gate 10. Thus, a PN code is outputted sequentially in the known mode from an output terminal of the exclusive OR circuit 6-4. When outputs Q1,Q2,...,Q9 of all the circuit stages of the shift register 4 are zero due to malfunction of the circuit or the like, that is, the output of the shift register 4 is all zero, the output of a NOR gate 8 goes to '1', and a data '1' is fed back to the 1st stage flip-flop 2-1 of the shift register 4 via the OR gate 10. Thus, the shift register 4 is escaped from the state of all zero, and the production of a PN(pseudo noise) code is implemented normally again afterward.