Title:
POWER CONSUMPTION ESTIMATION DEVICE AND METHOD
Document Type and Number:
Japanese Patent JP2004054756
Kind Code:
A
Abstract:
To provide a power consumption estimation device and method that can quickly and precisely estimate power consumption.
The power consumption estimation device comprises an operation synthesizer 2 and a clock base simulator 8. The operation synthesizer 2 captures an algorithm description to convert it into a clock base description and operation synthesis information. The clock base simulator 8 captures the clock base description and operation synthesis information to execute a clock base simulation and compute power consumption factors of storage elements from both clock base description and operation synthesis information.
Inventors:
SATO KOICHI
SHIBUYA HIROSHI
KUROSAKA HITOSHI
SHIBUYA HIROSHI
KUROSAKA HITOSHI
Application Number:
JP2002213912A
Publication Date:
February 19, 2004
Filing Date:
July 23, 2002
Export Citation:
Assignee:
NEC ELECTRONICS CORP
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Ken Ieiri