Title:
SYSTEM LEVEL DESIGN METHOD AND SYSTEM LEVEL DESIGN DEVICE
Document Type and Number:
Japanese Patent JP2004054755
Kind Code:
A
Abstract:
To automatically generate a description for clock base simulation.
In a system level design method, a codesign device 5 divides a hardware part and a software part of a system, and automatically generates a database including architecture information, mapping information and address information. From the database, information including the architecture information, mapping information and address information is next input into a top-level description generation device 9. According to the input information, the top-level description generation device 9 automatically generates a description for clock base simulation.
Inventors:
SATO KOICHI
SHIBUYA HIROSHI
KUROSAKA HITOSHI
SHIBUYA HIROSHI
KUROSAKA HITOSHI
Application Number:
JP2002213895A
Publication Date:
February 19, 2004
Filing Date:
July 23, 2002
Export Citation:
Assignee:
NEC ELECTRONICS CORP
International Classes:
G06F9/45; G06F17/50; G06G7/62; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Ken Ieiri
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