To provide a processor simulator capable of a high speed execution of simulation when a target program is simulated on a host processor and capable of debugging.
The processor simulator includes a code conversion creation means 2 for changing a first program described by the first instruction code of the direct executable machine language level on the target processor into the second program described by the second instruction code of a direct executable machine language level on the host processor, a debugging information display means 3 for displaying debugging information about the first program when the host processor simulates the second program, and an execution control means 3 for performing the control for simulating the second program by the host processor.
Toshimitsu Ichikawa
Kimihide Hashimoto