PRODUCING METHOD FOR SEMICONDUCTOR MEMORY DEVICE

Japanese Patent JP3841647

B2

PROBLEM TO BE SOLVED: To easily perform production for providing the large capacity and high integration degree of a capacitive storage part concerning a semiconductor memory device having the capacitive storage part.
SOLUTION: Upper layer wiring 16 is formed above a switching transistor provided on one part of a wafer 1. Further, a capacitive storage part 23 is formed above this upper layer wiring 16, and a capacitive storage part contact 18 is formed through the upper layer wiring 16. Thus, in the simultaneous patterning of upper layer wiring to a memory cell part and a peripheral circuit part, while keeping the capacity of a capacitive storage part 18 large, the degree of focus margin is kept great. Since the capacitive storage part contact 18 is made through a bit line 12, a drain 3 and a source 4 can be located symmetrically to a work line 6 similarly to the configuration of installation on the bit line and since a useless space is eliminated, the integration degree is further improved.

Tomofumi Shono
Masaki Fukumoto
Onishi Teruhito

JP2001049684A

November 01, 2006

December 03, 1992

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Matsushita Electric Industrial Co., Ltd

H01L21/3205; H01L27/108; H01L21/8242; H01L23/52; (IPC1-7): H01L27/108; H01L21/8242; H01L21/3205

JP1175756A
JP2094558A
JP4014867A
JP63278363A
JP4082262A
JP4225558A
JP3295270A

Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori

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