Title:
エッジデバイス上で機械学習演算を実施するためのプログラマブル回路
Document Type and Number:
Japanese Patent JP7157893
Kind Code:
B2
Abstract:
Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.
Inventors:
Yang, Hainin
chidambaram, periannan
chidambaram, periannan
Application Number:
JP2022511104A
Publication Date:
October 20, 2022
Filing Date:
August 26, 2020
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G06N3/063; G06G7/16; G06G7/60
Domestic Patent References:
| JP2016134515A |
Foreign References:
| US20180285006 |
Other References:
ROSSETTO O. et al.,Analog VLSI synaptic matrices as building blocks for neural networks,IEEE Micro [online],vol.9, no.6,1989年12月,pp.56-63,[2022年9月22日検索], インターネット
Attorney, Agent or Firm:
Masatoshi Kurata
Moriso Iseki
Takashi Okada
Moriso Iseki
Takashi Okada