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Title:
PROGRAMMABLE LOGIC ARRAY DEVICE WITH BUILTIN INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01218213
Kind Code:
A
Abstract:

PURPOSE: To early and easily attain the logical design and repair before a wiring stage in a manufacturing process by having an allowance at the number of input lines, the number of product item lines and the number of output lines necessary logically at the time of the design and constituting a necessary logic with the change of a wiring only.

CONSTITUTION: The title device is equipped with a decoder 19 to fully decode the input data of an input line 1, an AND plane part 20 to input a decoding line 3 and an OR plane part 21 to input a product item line 5. In the AND plane part 20, an AND plane part 0 cell 22 which becomes data '0' when the decoding line 3 is significant, and a plane part one cell 23, which becomes data '1' when the decoding line 3 is significant are embedded and in the same way, in the OR plane part 21, an OR plane part '0' cell 24 and an OR plane part '1' cell 25 is embedded. Only when the size of the device can be permitted, the number of the input lines 1, product item lines 5 and output lines 7 is increased, and to increased plane parts 20 and 21, cells 22 and 24 are embedded respectively.


Inventors:
HAMADA HIDEYUKI
Application Number:
JP4359688A
Publication Date:
August 31, 1989
Filing Date:
February 26, 1988
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/822; H01L21/82; H01L21/8234; H01L27/04; H01L27/08; H01L27/088; H03K19/177; (IPC1-7): H01L21/82; H01L27/04; H01L27/08; H03K19/177
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)



 
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