PURPOSE: To attain high speed operation by generating a 2nd clock signal in response to a clock signal from a clock signal generating means and the output of a dummy input line driving means and precharging a 2nd output line to a 1st reference level in response to the 2nd clock signal.

CONSTITUTION: Output signal lines on an AND plane 2b and an OR plane 4b are grouped by selecting two lines as a pair and reference potential signal lines CD1, CD2 are disposed in common to the two output signal lines in pairs. Moreover, a clock signal CLKOR for OR plane precharge control is generated in response to the signal potential of input signal lines ADB1, ADB2 of a dummy OR circuit 10 and a clock signal from an AND plane precharge control clock generating circuit 3b. Thus, the precharge/evaluation operation of the OR plane 4b is controlled in the optimum timing at all times and high speed operation is attained without generating a DC through-current in an output buffer without generating a malfunction.