Title:
PULSE GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED DEVICE MOUNTING IT
Document Type and Number:
Japanese Patent JP3667461
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To realize low power consumption by reducing undesired transition of a data bus.
SOLUTION: An input pulse signal XIN is given to a 1st delay circuit 16 and an intermediate signal TA is outputted to a 2nd delay circuit 18. An inverse of an output of the 2nd delay circuit 18 and the input pulse signal XIN are given to a 1st AND circuit 20, from which an intermediate signal TB is outputted. A 2nd AND circuit 22 receives intermediate signals TA, TB and outputs a pulse signal T1. A 3rd AND circuit 24 receives an inverse of the intermediate signal TA and the intermediate signal TB and outputs a pulse signal T2.
Inventors:
Eiichi Teraoka
Application Number:
JP23691896A
Publication Date:
July 06, 2005
Filing Date:
September 06, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F1/06; H03K3/02; H03K3/037; H03K5/15; (IPC1-7): H03K3/02; G06F1/06; H03K3/037; H03K5/15
Domestic Patent References:
| JP5046274A | ||||
| JP6152347A | ||||
| JP6310999A | ||||
| JP61264817A |
Attorney, Agent or Firm:
Hiroaki Tazawa
Konobu Kato
Hideaki Tazawa
Hamada Hatsune
Konobu Kato
Hideaki Tazawa
Hamada Hatsune
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