Title:
RECEPTION PROCESSING SYSTEM IN HDLC
Document Type and Number:
Japanese Patent JP3280816
Kind Code:
B2
Abstract:
PURPOSE: To realize a reception processing system in the HDLC in which access contention of reception data buffer read is suppressed and a system is built up efficiently.
CONSTITUTION: The system is made up of an HDLC reception processing section 10 receiving a frame in the information transmission unit used for the HDLC and processing the received frame according to the HDLC, an AC/I parting section 12 receiving data of A, C, I fields from the HDLC reception processing section 10, and parting the data into data 104 comprising the fields A, C, and I processed by a layer 3 processing unit and data 109 comprising data of the I field, and a reception data buffer 16 receiving and storing the data 104 from the AC/I parting section 12 and a reception data buffer 20 receiving and storing the data 108 from the AC/I parting section 12.
Inventors:
Yasuhiro Kudo
Go Ishizaki
Dr. Takenoshita
Kenichi Toya
Go Ishizaki
Dr. Takenoshita
Kenichi Toya
Application Number:
JP32232594A
Publication Date:
May 13, 2002
Filing Date:
December 26, 1994
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H04L29/08; H04L29/10; (IPC1-7): H04L29/10
Domestic Patent References:
| JP369244A |
Attorney, Agent or Firm:
Kenji Ohnishi
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