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Title:
RESETTING CIRCUIT OF DIGITAL DEVICE
Document Type and Number:
Japanese Patent JPS5616315
Kind Code:
A
Abstract:

PURPOSE: To prevent the abnormal operation of the digital device by using the resetting circuit which has a stable operation with the supplied voltage lower than the circuit voltage of the digital device.

CONSTITUTION: Even though the voltage of terminal 8 drops down to a level outside the control range of regulated power supply 7, the output voltage of regulated power supply 10 is stabilized by boosting circuit 13. And thus the voltage to be applied to variable resistance 16 is kept contstant. Accordingly, if the voltage of terminal 1 becomes lower than the reference voltage of comparator 11, monostable multivibrator 12 is turned on by the output of comparator 11 since the reference voltage of comparator 11 is set to the lower limit value by which digital device 6 can be able to have a normal operation by resistance 16. Thus capacitor 15 is discharged to generate the reset signal from terminal 5. After this, capacitor 15 is charged through resistance 14 when the voltage of terminal becomes higher than the reference voltage. And then monostable multivibrator 12 is turned off to release the reset signal after a delay time produced by the time constant. In such way, the abnormal operation can be prevented for the digital device.


Inventors:
MIYAMOTO ISAO
NAITOU SHIYUNICHI
Application Number:
JP9246579A
Publication Date:
February 17, 1981
Filing Date:
July 18, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K17/24; H03K3/02; (IPC1-7): H03K3/02



 
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