Title:
REVERSIBLE HEAT INSULATING LOGIC CIRCUIT AND PIPELINE REVERSIBLE HEAT INSULATING LOGIC DEVICE USING SAME
Document Type and Number:
Japanese Patent JP3852071
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a reversible heat insulating logic circuit which compensates a swing decrease due to a threshold voltage by using a pair of PMOS transistors(TRs) by compensating the swing decrease from an output node due to the threshold voltage by a normal logical function circuit and a reverse logical function circuit.
SOLUTION: A compensating circuit 35 has a 1st PMOS TR QP1 which has its drain and source connected to the output of a normal logical function calculation part 311 and a clock &phiv 1, a 2nd PMOS TR QP2 which has its gate connected to the gate of the 1st PMOS TR QP1 and its drain and source connected to the output of a reverse logical function calculation part 331 and a clock &phiv 3, and a 3rd PMOS TR QP3 which has its drain and source connected to the output of a phase correcting logical function calculation part 313 and the clock &phiv 1. Consequently, a nonadiabatic loss can be removed.
Inventors:
Xue Yi
Application Number:
JP2000112984A
Publication Date:
November 29, 2006
Filing Date:
April 14, 2000
Export Citation:
Assignee:
Daewoo Electronics Corporation
International Classes:
G06F1/04; H03K19/173; G06F7/50; G06F7/501; H03K19/00; H03K19/0175; H03K19/096; (IPC1-7): H03K19/173; G06F1/04; H03K19/096
Domestic Patent References:
JP8335873A |
Foreign References:
US5602497 |
Other References:
W.C.Athas他,「Low Power Digital Systems Based on Adiabatic-Switching Principles」,IEEE Transactions on Very Large Scale Integration(VLSI) Systems,米国,IEEE,1994年12月,Vol.2, No.4,pp398-407,断熱充電回路
Attorney, Agent or Firm:
Eiji Saegusa
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
Kakehi Yuro
Takeshi Ohara
Hiroji Nakagawa
Yasumitsu Tate
Kenji Saito
Jun Fujii
Hitoshi Seki
Mutsuko Nakano
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