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Patent Searching and Data


Title:
SC BIT SUPERIMPOSING SYSTEM
Document Type and Number:
Japanese Patent JPS5856554
Kind Code:
A
Abstract:

PURPOSE: To perform the superimposition of SC-bit based on a purely logical method, by superimposing the SC-bit on a code signal through the use of a pair of the code signals, in a PCM communication system with mB and nB codes.

CONSTITUTION: Original signals 3B of 2B sets consisting of m(=3) bits are represented with any pairs of 2B sets consisting of code signals 5B of two n(=5) bits corresponded respectively. A part of the pairs has the same disparity and the other pairs have the same disparity reducing the sum of one displarity and the other disparity to zero for any combination of the pairs. In superimposing the SC bit on the code signals 5B, the logic 1 of the SC bit is superimposed by outputting one and the other of the corresponding code signals 5B alternately for X-times and the logic 0 of the SC bit can be superimposed by alternately outputting one and the other of the corresponding code signals 5B for Y-times.


Inventors:
GOTOU MASAYUKI
Application Number:
JP15509781A
Publication Date:
April 04, 1983
Filing Date:
September 30, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M7/14; H04L25/49; (IPC1-7): H04L25/49
Attorney, Agent or Firm:
Aoki Akira