To reduce a test time.

This integrated circuit device has plural scan cells. Each scan cell has a scan flip-flop 21 and a selection circuit 31 for selecting one of the signals of a scan-in end SI and a scan-out end SO of the scan flip-flop 21 according to a selection control signal to feed it to a cell output end. The plural scan cells are connected in a cascade from in relation to the respective scan-in ends DI and cell output ends, and a clock signal is fed to clock input ends C of the respective scan flip-flops. By defining the selection control signal value by a bypass control shift register 45, bypasses are formed between a scan data input terminal SDI and the SI of an arbitrary scan flip-flop other than one at the first stage and/or between the SO of an arbitrary scan flip-flop other than one at the last stage and a scan data output terminal SDO.