SEMICONDUCTOR ARITHMETIC CIRCUIT, AND DTA PROCESSOR

Title:

SEMICONDUCTOR ARITHMETIC CIRCUIT, AND DTA PROCESSOR

Document Type and Number:

Japanese Patent JPH10260817

Kind Code:

A

Abstract:

To compare the sizes of plural pieces of data at a high speed by using a simple circuit in real time, by specifying a position where maximum voltage exists among signal voltage inputted to an inverter circuit group by the output signal of the inverter circuit group.

Since a vMOS(vertical MOS) cell B221 maintains an inversion state when '1' is inputted to even one of V1-V4, VR continuously reduces until the output of the last vMOS cell A218 changes from '1' to '0'. When the output of the vMOS cell A218 becomes '0', the vMOS cell B221 inverts the state and VR starts increasing to '1'. Since VR is decided so that the vMOS cell A218 of maximum input oscillates near a threshold, the oscillation of the circuit is formed to always contain the vMOS cell A218 of maximum input. Thus, the position of largest input voltage can continuously in time be specified.

Inventors:

MORIMOTO TATSURO
SHIBATA SUNAO
OMI TADAHIRO

Application Number:

JP8187797A

Publication Date:

September 29, 1998

Filing Date:

March 15, 1997

Export Citation:

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Assignee:

SHIBATA SUNAO
OMI TADAHIRO

International Classes:

G06F7/02; G06G7/12; G06N3/063; H01L21/8247; H01L27/115; H01L29/78; H01L29/788; H01L29/792; H03K19/20; (IPC1-7): G06F7/02; H01L27/115; H01L29/78; H01L21/8247; H01L29/788; H01L29/792; H03K19/20

Attorney, Agent or Firm:

Fukumori Hisao

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