Title:
SEMICONDUCTOR ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3503772
Kind Code:
B2
Abstract:
PURPOSE: To obtain a semiconductor device in which a voltage waveform in which many functions are similar to a folding line can be generated with low power consumption by controlling ON and OFF of a MOS transistor by a floating gate in which the output voltage of a first or second circuit is coupled via a capacitor.
CONSTITUTION: When a first signal voltage is lower than a first voltage value with respect to the first signal voltage decided as a single analog input voltage or the weighted mean voltage of a plurality of analog input voltages, a predetermined second voltage value is output, while when it is larger than the first voltage value, a predetermined first voltage value is output. A plurality of one or both of such a first circuit and a second circuit having reverse relation of the output to the first circuit are used. In such a semiconductor circuit 153, the output voltage of the first or second circuit is electrically coupled to the same floating gate via a capacitor and the floating gate controls ON or OFF of at least the one MOS transistor.
Inventors:
Ryu Kaibara
Naoshi Shibata
Tadahiro Ohmi
Naoshi Shibata
Tadahiro Ohmi
Application Number:
JP7693095A
Publication Date:
March 08, 2004
Filing Date:
March 31, 1995
Export Citation:
Assignee:
Naoshi Shibata
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
International Classes:
G06G7/60; H01L21/8247; H01L29/788; H01L29/792; H03K19/20; (IPC1-7): H01L21/8247; G06G7/60; H01L29/788; H01L29/792; H03K19/20
Domestic Patent References:
| JP6244375A | ||||
| JP5335506A |
Attorney, Agent or Firm:
Hisao Fukumori