Title:
SEMICONDUCTOR CHIP AND EVALUATION METHOD
Document Type and Number:
Japanese Patent JP2005109393
Kind Code:
A
Abstract:
To provide a semiconductor chip with which multi-level interlayer insulating film can be evaluated.
In order to detect the peeling between an interlayer insulating film and a wiring layer, an interlayer peeling evaluation structure is formed, in which resistance elements are formed respectively on a plurality of interlayer insulating films, and are parallel-connected by via wiring. The structures are arranged on semiconductor chip positions where the peeling is easier to occur as compared to inside circuits. By monitoring the resistance value of the parallel-connected resistance elements, the peeling position can be detected or specified.
Inventors:
MURAKAMI HIROKO
Application Number:
JP2003344291A
Publication Date:
April 21, 2005
Filing Date:
October 02, 2003
Export Citation:
Assignee:
NEC ELECTRONICS CORP
International Classes:
H01L21/3205; H01L21/768; H01L21/822; H01L23/52; H01L23/522; G01R31/26; H01L27/04; (IPC1-7): H01L21/822; G01R31/26; H01L21/3205; H01L21/768; H01L27/04
Attorney, Agent or Firm:
Yosuke Goto
Kenho Ikeda
Kenho Ikeda