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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MANUFACTURING APPARATUS
Document Type and Number:
Japanese Patent JP2005109392
Kind Code:
A
Abstract:

To provide a semiconductor manufacturing apparatus which can cope with leadframe misalignment while reducing the time for recognizing the characteristic pattern of a die pad.

The characteristic pattern of a first die pad is recognized by moving a bonding camera to a position on data (the position indicated by a first virtual position data). A semiconductor chip is mounted on the die pad, on the basis of the position data that indicates the actual position of the recognized characteristic pattern (S101-S106). Successively, the bonding camera is moved from the position on data (the position indicated by a second virtual position data) of the characteristic pattern of a second die pad to a position displaced by an amount that reflects the recognition result of the first die pad (S108). Next, the characteristic pattern of the second die pad is recognized (S109). The search area for recognition is made narrower than that in the case in which the characteristic pattern of the first die pad is recognized.


Inventors:
FUJIMORI HIROYUKI
KOBASHI HIDEHARU
MUKIIWA KAZUTAKA
Application Number:
JP2003344285A
Publication Date:
April 21, 2005
Filing Date:
October 02, 2003
Export Citation:
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Assignee:
RENESAS TECH CORP
RENESAS E JP SEMICONDUCTOR INC
International Classes:
H01L21/52; (IPC1-7): H01L21/52
Attorney, Agent or Firm:
Yamato Tsutsui