Title:
半導体回路構造
Document Type and Number:
Japanese Patent JP4167228
Kind Code:
B2
Abstract:
The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.
Inventors:
Brassiere,gabriella
Austermayer, Martin
Ruderer, Elven
Austermayer, Martin
Ruderer, Elven
Application Number:
JP2004557778A
Publication Date:
October 15, 2008
Filing Date:
November 27, 2003
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L21/3205; H01L21/768; H01L29/06; H01L29/417
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita