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Patent Searching and Data


Title:
SEMICONDUCTOR DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH03267812
Kind Code:
A
Abstract:

PURPOSE: To delay a signal by an object delay signal even when a period of an external clock signal is largely changed by adding or eliminating a delay circuit depending on the period of the external clock signal.

CONSTITUTION: The circuit consists of an external clock signal terminal 1, an input terminal 2, an output terminal 3, delay circuits 4-9, selector circuits 10,11, a phase comparator circuit 12, voltage comparator circuits 13,14, ground terminals 17, 18 and a control circuit 19, the external clock signal terminal 1 connects to the delay circuit 4 and the phase comparator circuit 12, the delay circuit 4 connects to the delay circuit 5 and the selector circuit 10, the delay circuit 5 connects to the delay circuit 6 and the selector circuit 10, the delay circuit 6 is connected to the selector circuit 10, and the selector circuit 10 is connected respectively to the phase comparator circuit 12. In this case, the delay circuits 4-9 are added or removed before the control range by the delay circuits 4-9. Even when the period of the external clock signal is largely changed, the delay circuits 4-9 are controlled and the signal delay is varied by an object delay time.


Inventors:
OKADA YOSHIAKI
Application Number:
JP6651890A
Publication Date:
November 28, 1991
Filing Date:
March 16, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K5/135; H03H11/26; (IPC1-7): H03H11/26; H03K5/135
Attorney, Agent or Firm:
Uchihara Shin