PURPOSE: To increase charge-voltage conversion gains, and to improve S/N by forming a P-channel junction type FET for amplifying charges and an N- channel junction type FET for reset in the same island region surrounded by an isolation region.
CONSTITUTION: A P-type source region 21, a P-type drain region 31, an N-type gate region 41, a P-type region 51 as a channel and an N+ type buried layer 60 constituting a P-FETQ1 for amplifying charges are shaped in a single N-type island region 12 surrounded by a P-type isolation region 11 while an N+ type drain region 32 and a P-type gate region 42 organizing an N-FETQ2 for reset are formed. Accordingly, parasitic capacitance with wiring can be removed, and parasitic capacitance among a substrate and the gate regions can also be reduced.
MIYAGUCHI KAZUHISA
MURAKI TETSUHIKO
| JPS62296467A | 1987-12-23 | |||
| JPS60247956A | 1985-12-07 | |||
| JPS61267358A | 1986-11-26 | |||
| JPS60223161A | 1985-11-07 |