Title:
半導体装置の解析及び設計装置、及び半導体装置の解析及び設計方法
Document Type and Number:
Japanese Patent JP5405055
Kind Code:
B2
Abstract:
An analysis and design apparatus for semiconductor device, which utilizes a transistor model using accurate channel impurity concentration distribution are provided. The analysis and design apparatus includes a parameter setting portion that divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. Further, the analysis and design apparatus includes an element characteristic calculation portion that values of electric characteristics of the transistor using surface potential that is calculated by solving a Poisson equation using a plurality of effective impurity concentrations. Moreover, the determination portion compares the calculated values with measured values read from a storage portion based on the structure information, and determines that the plurality of parameters for the transistor when the measured values correspond to the calculated values.
Inventors:
Hironori Sakamoto
Application Number:
JP2008159702A
Publication Date:
February 05, 2014
Filing Date:
June 18, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/336; G06F17/50; H01L29/00; H01L29/78
Domestic Patent References:
| JP9148563A | ||||
| JP2005340340A |
Attorney, Agent or Firm:
Minoru Kudo