Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2002289704
Kind Code:
A
Abstract:
To achieve the desired value of a breakdown voltage between well regions by making the junction breakdown voltage of an N-well region for forming a MOSFET, which is formed in a P type silicon substrate and is a high breakdown voltage system of higher than the order of 25 [V], higher and by slightly separating adjacent N-well regions.
In a semiconductor device having two or more adjacent N-well regions 107 that sandwich the region of a prescribed width on the P type silicon substrate 101, a P-well region 108 is provided via offset regions A for the adjacent N-well regions.
More Like This:
Inventors:
ARAI NORIHISA
KAMIYA EIJI
KAMIYA EIJI
Application Number:
JP2001084992A
Publication Date:
October 04, 2002
Filing Date:
March 23, 2001
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA MICRO ELECTRONICS
TOSHIBA MICRO ELECTRONICS
International Classes:
H01L21/8247; H01L21/8238; H01L27/092; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L21/8238; H01L27/092; H01L27/10; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)