Title:
SEMICONDUCTOR DEVICE AND LAYOUT DESIGN METHOD
Document Type and Number:
Japanese Patent JP2015037141
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent a design period from being prolonged by retrial of the design for timing adjustment.SOLUTION: A semiconductor device 20 is laminated on a semiconductor chip 30 and includes a plurality of first to fourth power supply wiring E1 to E4 which are provided at positions opposite to each other in a plan view. The first to fourth power supply wiring E1 to E4 include: first to fourth power source trunk lines which are formed in a non-annular state and continuously formed in a single-stroke writing manner and which are connected to power source terminals 31, 32, 33, 34 respectively; and a plurality of first to fourth branch wiring which are connected to the first to fourth power source trunk lines and which spread on the semiconductor 30 from different positions of the first to fourth power source trunk lines.
Inventors:
MIZUNO SHIGEKI
TADA HIROYUKI
TADA HIROYUKI
Application Number:
JP2013168679A
Publication Date:
February 23, 2015
Filing Date:
August 14, 2013
Export Citation:
Assignee:
FUJITSU SEMICONDUCTOR LTD
International Classes:
H01L21/82; G06F17/50; H01L21/3205; H01L21/768; H01L21/822; H01L23/522; H01L27/04
Attorney, Agent or Firm:
Makoto Onda
Hironori Onda
Hironori Onda
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