To provide a semiconductor device manufacturing method in which a misalignment problem with wiring of an upper wiring layer does not arise when forming an opening for a through electrode.
A semiconductor device manufacturing method includes a step of preparing a substrate having a first surface and a second surface on the opposite side of the first surface, a step of forming a sacrifice film pattern on a region in which a through electrode extending from the first surface of the substrate in a thickness direction of the substrate is to be formed, a step of forming an upper wiring layer which is formed on the first surface of the substrate and has wiring located on the sacrifice film pattern, a step of exposing the sacrifice film pattern by partially removing the second surface of the substrate, a step of forming an opening which exposes the wiring by removing the sacrifice film pattern from the second surface of the substrate and a step of forming, in the opening, the through electrode electrically connected with the wiring.
| JP2695812 | [Title of Invention] Semiconductor device |
| JP2009111073 | SEMICONDUCTOR DEVICE |
| JP2000003960 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE |
SAI KICHIGEN
BANG SEOK-CHOL
MOON KWANG-JIN
LIM DONG-CHAN
JUNG DUK YOUNG
| JP2006060067A | 2006-03-02 | |||
| JP2005294577A | 2005-10-20 | |||
| JP2006173637A | 2006-06-29 | |||
| JP2009515354A | 2009-04-09 | |||
| JP2009164481A | 2009-07-23 |
| WO2010035379A1 | 2010-04-01 | |||
| WO2010035379A1 | 2010-04-01 |