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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND THE MANUFACTURING PROCESS
Document Type and Number:
Japanese Patent JPS5626467
Kind Code:
A
Abstract:

PURPOSE: To facilitate control of a transistor's electrical properties and also to provide a strong resistance against contamination from outside, by embedding an MOS transistor constituting gate electrode into a semiconductor substrate.

CONSTITUTION: An SiO2 membrane 2 is attached onto a P type Si substrate 1, a resist membrane 3 having a prescribed opening is provided on the membrane 2, and an N type impurity is injected through the membrane 2 which is exposed in the opening and then heat-treated to be activated, so than an N type gate electrode 4 is formed. By doing so, a gate electrode 4 is formed by being embedded into the substrate 1, an amorphous Si membrane 5 is made to grow on the membrane 2 and unnecessary portions on the surrounding area are oxidized to be turned into an SiO2 membrane 6. And then, a resist membrane 7 is provided on the membrane 5 remaining on the other side of the electrode 4, an N type impurity ion is injected with the membrane 7 as a mask and heat-treated to form an N type source and a drain region 9 in the membrane 5, and a channel region 8 is formed between these regions. And then, an entire surface is covered with an SiO2 membrane 10 and provided with an opening, and an aluminum wiring 12 is attached onto the region 9.


Inventors:
MIZUTANI YOSHIHISA
Application Number:
JP10119279A
Publication Date:
March 14, 1981
Filing Date:
August 10, 1979
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/265; H01L21/336; H01L21/74; H01L21/762; H01L23/522; H01L29/417; H01L29/78; H01L29/786; (IPC1-7): H01L29/04; H01L29/58
Domestic Patent References:
JPS503787A1975-01-16