To provide a semiconductor device with its quality and reliability enhanced by reducing the region of a sealing resin 6 along the edges of a semiconductor element 2 for stress alleviation along the edges.
The semiconductor device comprises a semiconductor device carrier 3 which is an insulating substrate having on its top surface a wiring pattern connected to a plurality of electrodes 4 and, on its bottom surface, external connection terminals 7 electrically connected to the electrodes 4 and to wirings; a semiconductor element 2 connected by a plurality of bump electrodes to the electrodes 4 on the top surface of the semiconductor device carrier 3; and a sealing resin 6 for filling and coating gaps between the semiconductor element 2 and the semiconductor device carrier 3, and for providing a coating along the edges of the semiconductor element 2. Of the sealing resin 6 coating the semiconductor device carrier 3 along the edges of the semiconductor element 2, the part coating one of the edges is cut off for the cross section of the sealing resin 6 to be roughly vertical to the surface of the semiconductor device carrier 3.
AKABOSHI TOSHITAKA
NAKAOKA YUKIKO
KAWAKAMI YOSHIHIKO
ITO SEIICHI
