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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2013191898
Kind Code:
A
Abstract:

To provide a semiconductor device that allows preventing the occurrence of voids in a sealing layer.

A semiconductor device 1 includes a wiring board 2 and a semiconductor chip 3 connected to a first surface 2a of the wiring board 2 so that its function surface 3a is faced to the first surface 2a. On the first surface 2a of the wiring board 2, a rectangular connection pad is formed, the wiring board 2 and the semiconductor chip 3 are bonded by a connection member 5 connected to the connection pad so as to maintain a predetermined interval, and they are electrically connected to each other. On the first surface 2a of the wiring board 2, a solder resist film 6 is formed. In the solder resist film 6, an opening 6a having a larger size than the semiconductor chip 3, namely, formed so that the semiconductor chip 3 is entirely included therein, is provided in a planar view vertically looking down the surface 2a. A step is not formed in the opening 6a except for a step provided on the first surface 2a of the wiring board 2 and formed by wiring connected to the connection member 5.


Inventors:
TANIDA KAZUMA
MIYATA OSAMU
Application Number:
JP2013140884A
Publication Date:
September 26, 2013
Filing Date:
July 04, 2013
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
H01L23/12; H01L21/60; H01L23/29; H01L23/31; H01L25/04; H01L25/18
Domestic Patent References:
JPH09153519A1997-06-10
JPH11214586A1999-08-06
JPH06283561A1994-10-07
JP2002043352A2002-02-08
JP2004014651A2004-01-15
JP2001185653A2001-07-06
Foreign References:
WO2009116202A12009-09-24
Attorney, Agent or Firm:
Inaoka cultivation
Mio Kawasaki
Kyoumura Junji



 
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