Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2014150481
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To achieve, by simple manufacturing processes, a semiconductor device which can perform power gating with a small area.SOLUTION: A semiconductor arithmetic device 1 comprises a power switch 7 for shutting down (power gating) the power supply to a logic circuit block in a standby state out of a plurality of logic circuit blocks 30. The power switch 7 includes a plurality of transistors 70 connected in parallel between a virtual ground line 6 and a ground voltage GND. The plurality of transistors 70 are formed on an upper surface of a semiconductor integrated circuit 80 where a plurality of the logic circuit blocks 30 are formed, and are composed of thin-film transistors in which an oxide semiconductor is used as a channel layer.
Inventors:
ISHIHARA KAZUYA
Application Number:
JP2013019278A
Publication Date:
August 21, 2014
Filing Date:
February 04, 2013
Export Citation:
Assignee:
SHARP KK
International Classes:
H03K19/00; H01L21/822; H01L21/8234; H01L21/8238; H01L27/04; H01L27/08; H01L27/088; H01L27/092; H01L29/786
Domestic Patent References:
| JP2012094171A | 2012-05-17 | |||
| JP2011142314A | 2011-07-21 | |||
| JP2002158576A | 2002-05-31 | |||
| JP2008085571A | 2008-04-10 | |||
| JP2012257187A | 2012-12-27 |
Attorney, Agent or Firm:
Patent business corporation Fukami patent firm