Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2014160536
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To reduce variation in the operation timing in a semiconductor device having a memory unit.SOLUTION: For example, a semiconductor device has dummy bit lines DBL1 and DBL2 arranged in parallel with a normal bit line BL and column direction load circuits CLBn[1] to CLBn[x] which are sequentially connected on DBL1 and DBL2. Each column direction load circuit has a plurality of NMOS transistors MNa1 to MNa4 which are fixed in an off state, among which a source and a drain of MNa2 and MNa3 are appropriately connected to DBL1 or DBL2. A load capacity due to a diffusion layer capacitance of MNa2 and MNa3 is applied to DBL1 and DBL2 and accordingly a delay time from a decode start signal TDEC to a dummy bit line signal SDBL is set. SDBL is used in determining a startup timing of a sense amplifier.
Inventors:
TANAKA SHINJI
YABUUCHI MAKOTO
YOSHIDA YUTA
YABUUCHI MAKOTO
YOSHIDA YUTA
Application Number:
JP2014094761A
Publication Date:
September 04, 2014
Filing Date:
May 01, 2014
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G11C11/419; G11C11/412
Domestic Patent References:
| JP2000156085A | 2000-06-06 | |||
| JP2002298585A | 2002-10-11 | |||
| JPH11306787A | 1999-11-05 | |||
| JP2001521262A | 2001-11-06 |
Attorney, Agent or Firm:
Tsutsui Daiwa
Atsushi Sugata
Akiko Tsutsui
坂次 Tetsuya
Atsushi Sugata
Akiko Tsutsui
坂次 Tetsuya