Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2014203841
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To resolve a problem that a bypass is generated in a wiring layer in a case where gate electrodes of a plurality of vertical transistors are connected by the wiring layer formed on a lateral face of an insulator pillar, which causes rise in resistance of a current path to the gate electrodes.SOLUTION: A wiring layer connected with gate electrodes of vertical transistors is configured by pillar outer peripheral wiring parts electrically connected with each other, and an electrode wiring part connected with the gate electrodes of the vertical transistors, provided on lateral faces of a plurality of divided insulator pillars. Thereby, the wiring layer connected to the gate electrodes becomes in a commonly-connected state each time passing through the insulator pillar, and a resistance value resulting from the gate electrode wiring can be reduced.
Inventors:
ENDO KIYOTAKA
ISHIZUKA KAZUTERU
ISHIZUKA KAZUTERU
Application Number:
JP2013076034A
Publication Date:
October 27, 2014
Filing Date:
April 01, 2013
Export Citation:
Assignee:
PS4 LUXCO SARL
International Classes:
H01L27/092; H01L21/3205; H01L21/336; H01L21/768; H01L21/82; H01L21/822; H01L21/8238; H01L21/8242; H01L23/522; H01L27/04; H01L27/108; H01L29/423; H01L29/49; H01L29/78
Attorney, Agent or Firm:
Noriyasu Ikeda
Shuichi Fukuda
Takashi Sasaki
Shuichi Fukuda
Takashi Sasaki