Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3459017
Kind Code:
B2
Abstract:

PURPOSE: To constitute an association memory by an extremely simple circuit constitution to perform operation of size comparison of a plurality of data and sequencing regarding the size at high speed by using inverter circuits composed of neuron MOS transistors.
CONSTITUTION: This semiconductor device has inverter circuits 116, 136 composed of newlon MOS transistors 102, 103, 122, 123. Then, in these circuits, the ON-OFF states of the gates of NMOS 112, 113, 132, 133 are inverted in the process of changing VR from 0V to 5V by inputting signal voltage from an input gate 151 and Vc values at those moments are memorized by the memories in these circuits. When VINB is larger than VINA, VAOUT=5V, VBOOT=OV are memorized by flipflop and when VINA is larger than VINB, VAOUT=OV, VBOOT=5V are memorized. Thereby, the relative sizes of two values can be discriminated by reading the signals memorized by flipflop after sweeping VR from 0 to 5V.


Inventors:
Takeo Yamashita
Naoshi Shibata
Tadahiro Ohmi
Application Number:
JP3102093A
Publication Date:
October 20, 2003
Filing Date:
February 22, 1993
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Naoshi Shibata
Tadahiro Ohmi
UCT Co., Ltd.
I&F Co., Ltd.
International Classes:
G06F7/02; G06F7/24; G06G7/60; G06N3/063; G11C15/04; H01L27/10; H03K19/00; H03K19/0948; (IPC1-7): H01L27/10; G06F7/24; G06G7/60; H03K19/00; H03K19/0948
Domestic Patent References:
JP653431A
JP4271486A
JP36679A
Other References:
1991 IEDM Technical Digest, 1991年, pp.919−922
1992 IEDM Technical Digest, 1992年, pp.431−434
1993 ISSCC Digest of Technical Papers, 1993年, pp.236−237,294
Electronics Letters, Vol.27,No.11, pp.957−958
IEEE Transactions on Electron Devices, Vol.39, No.6, pp.1444−1455
電子情報通信学会技術研究報告, Vol.DSP−93, No.233, pp.31−38
Attorney, Agent or Firm:
Hisao Fukumori