Title:
半導体装置
Document Type and Number:
Japanese Patent JP6806597
Kind Code:
B2
Abstract:
The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data. A reference memory cell is configured to generate a reference current corresponding to reference data. A first circuit is configured to generate and hold a third current corresponding to the difference between the first current and the reference current when the first current is lower than the reference current. A second circuit is configured to generate and hold a fourth current corresponding to the difference between the first current and the reference current when the first current is higher than the reference current. One of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data.
Inventors:
Yoshimoto Kurokawa
Application Number:
JP2017044502A
Publication Date:
January 06, 2021
Filing Date:
March 09, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/12
Domestic Patent References:
| JP6274661A | ||||
| JP4067259A | ||||
| JP2012150875A |
Foreign References:
| US20050122238 |