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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH02246516
Kind Code:
A
Abstract:

PURPOSE: To obtain a fast, low-noise semiconductor device low in power consumption by operating the majority of circuits in a chip with a low amplitude and driving an MOS memory cell with a signal which is converted by a level converting circuit to a high amplitude.

CONSTITUTION: The input circuit and output circuit of the input circuit of an ECL/TTL interface are composed of bipolar or BiCOMS circuits and operated with a source voltage (VCC, VEE) which is applied from outside. An internal logic circuit or memory is composed of a CMOS circuit and operated with an internal source voltage VC1 or VE1, so this internal circuit receives an input signal of 0.8-1.6V from the input circuit to operate fast with the low amplitude. Voltage converting circuits L1 and L2 generate the voltage VC1 and VE1 which are lower than the VCC and higher than the VEE by using MOS or bipolar transistors. Thus, the majority of CMOS circuits of the chip is operated with the low voltage, so the fast, low in power consumption and low-noise semiconductor device is obtained.


Inventors:
KAWAHARA TAKAYUKI
KITSUKAWA GORO
KAWAJIRI YOSHIKI
ITO KIYOO
Application Number:
JP6612889A
Publication Date:
October 02, 1990
Filing Date:
March 20, 1989
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/409; G11C5/14; G11C7/10; G11C8/06; G11C8/08; G11C8/10; G11C11/401; G11C11/407; G11C11/4074; H01L27/10; H03K19/0175; (IPC1-7): G11C11/401; G11C11/409; H01L27/10; H03K19/0175
Domestic Patent References:
JPS63302622A1988-12-09
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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