Title:
半導体装置及び三次元実装半導体装置
Document Type and Number:
Japanese Patent JP4145301
Kind Code:
B2
Abstract:
A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
Inventors:
Eiji Yoshida
Takao Ohno
Yasuto Akutagawa
Koji Sawahata
Masataka Mizukoshi
Takao Nishimura
Akira Takashima
Mitsuhisa Watanabe
Takao Ohno
Yasuto Akutagawa
Koji Sawahata
Masataka Mizukoshi
Takao Nishimura
Akira Takashima
Mitsuhisa Watanabe
Application Number:
JP2004566268A
Publication Date:
September 03, 2008
Filing Date:
January 15, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L25/065; H01L21/3205; H01L21/768; H01L23/31; H01L23/48; H01L23/485; H01L23/52; H01L23/522; H01L25/07; H01L25/18; H01L29/76
Domestic Patent References:
| JP8213427A | ||||
| JP2001177041A | ||||
| JP2001307057A | ||||
| JP2000049277A | ||||
| JP2002050735A | ||||
| JP2002305283A |
Attorney, Agent or Firm:
Tadahiko Ito