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Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH04237142
Kind Code:
A
Abstract:

PURPOSE: To make possible the improvement of reliability of the assembly of a multipin LSI and the improvement of the yield of the LSI by a method wherein the LSI is provided with bonding pad parts and pads for wafer probing test use, which are connected to the bonding pad parts.

CONSTITUTION: Bonding pads B1 to Bn are provided on the inside of a scribing line C and pads A1 to An for wafer probing test use are provided on the outside of the line C. The pads, which respectively make a pair among the pads B1 to Bn and the pads A1 to An, are connected to each other via a metallized wiring. When an electrical selection is performed on a wafer, probes are brought into contact to the pads A1 to An and a decision on the good or bad of the pads A1 to An is executed. Thereby, the reliability of the assembly of a multipin LSI and the yield of the LSI can be improved.


Inventors:
ICHIMURA ISAO
Application Number:
JP553991A
Publication Date:
August 25, 1992
Filing Date:
January 22, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Attorney, Agent or Firm:
Shin Uchihara