Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS634669
Kind Code:
A
Abstract:

PURPOSE: To flatten the surface of a capacitance element, and to increase a capacitance value by burying each layer of a first conductive layer, a dielectric film and a second conductive layer into a thin groove or a thin hole approximately completely.

CONSTITUTION: A thin groove 3A is constituted in width size W the same as or smaller than size of twice as large as film thickness T1 in which each of a conductive layer 4A, a dielectric film 4B and a conductive layer 4C are superposed (2T1≥W). That is, respective layer of the conductive layer 4A, the dielectric film 4B and the conductive layer 4C is buried into the thin groove 3A completely or approximately completely, and the surface (actually, the surface of the conductive layer 4C) of a capacitance element C is flattened. The thin groove 3A is organized in width size W larger than size of twice as large as film thickness T2 in which each of the conductive layer 4A and the dielectric film 4B is superposed (2T2<W). That is, three layers of the conductive layer 4A, the dielectric film 4B and the conductive layer 4C are constructed along the shape (a stepped shape) of the thin groove 3A in the thin groove 3A, thus increasing the area of the capacitance element C in the direction vertical to the main surface of a semiconductor substrate 1, then elevating the capacitance value of the capacitance element C.


Inventors:
HORIUCHI MITSUAKI
TADAKI YOSHITAKA
Application Number:
JP14687286A
Publication Date:
January 09, 1988
Filing Date:
June 25, 1986
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H01L27/10; H01L21/8242; H01L27/108; (IPC1-7): H01L27/10
Attorney, Agent or Firm:
Katsuo Ogawa