Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4246243
Kind Code:
B2
Abstract:
In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
Inventors:
Yujiro Kajiwara
Kazushige Suzuki
Kunihiro Tsubosaki
Suzuki Hiromichi
Miyanori Yoshinori
Takahiro Naito
Kawai Sueo
Kazushige Suzuki
Kunihiro Tsubosaki
Suzuki Hiromichi
Miyanori Yoshinori
Takahiro Naito
Kawai Sueo
Application Number:
JP2007219888A
Publication Date:
April 02, 2009
Filing Date:
August 27, 2007
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L23/50; H01L21/48; H01L21/52; H01L21/60; H01L23/495
Domestic Patent References:
| JP4311062A | ||||
| JP3209755A | ||||
| JP3032048A |
Attorney, Agent or Firm:
Yamato Tsutsui
Previous Patent: 半導体発光素子
Next Patent: PRESSURIZING FLUIDIZED BED COMBINED PLANT AND PARTIAL LOAD OPERATION CONTROL AND DEVICE THEREFOR
Next Patent: PRESSURIZING FLUIDIZED BED COMBINED PLANT AND PARTIAL LOAD OPERATION CONTROL AND DEVICE THEREFOR